1. Field of the Invention
The present invention relates to the synchronization of receivers which receive digitally encoded transmissions including orthogonal signals.
2. Description of the Prior Art
The 3GPP TS 25.211 v4.0.0 (2001-03) Technical Specification in Release 4 contains a description of group radio access network physical channels and mapping of transport channels onto the physical channels. Section 5.3.3.5 therein entitled “Synchronisation Channel (SCH)” describes the synchronization channel of the group radio access network as having two subchannels which are the primary and the secondary channels. The primary channel is described as having 15 repeating slots. Each slot contains a synchronization symbol acp consisting of I and Q signals which are each encoded with a unique sequence of 256 chips in length. Each slot is a total of 2,560 chips in length. The remainder of the slot contains data symbols. The detection of the unique code for each of the I and Q signals by the receiver's demodulator is used to synchronize the receiver with the time base of the transmitter.
FIG. 1 illustrates a prior art demodulator used for detecting the primary channel synchronization code as described above. The demodulator 10 is only partially shown with I and Q signals from each detected synchronization symbol being provided as inputs thereto from known circuitry which is not illustrated. The I and Q signals are applied to first and second well-known identical Golay detectors 12 which are each comprised of a series of connected fixed delays D1–D8 and adders 16. As illustrated, Table 14 defines the relative delays as a function of the oversampling factor (OSF). The adders 16 are disposed between various inputs and outputs of the delays to produce products of the delayed signals.
Each of the Golay detectors 12 responds to its respective I and Q signal inputs which consist of M chips, e.g. 256 as described in the aforementioned 3GPP publication which is incorporated herein by reference in its entirety to produce a single high chip within the 256 chips of each of the orthogonal synchronization signals. The high chip from each Golay detector 12 precisely marks the time base to which the demodulator of the receiver is synchronized.
The series of connected delays D1–D8 and adders 16 produce output I and Q signals 18 and 20 which include the aforementioned chip which is high marking the time base of synchronization. The signals 18 and 20 are supposed to be high for only one chip during the synchronization slot which is detected by Golay detectors 12. However, during the remaining nine symbols of each slot, during which data is transmitted, the outputs 18 and 20 are supposed to be low and should not produce any synchronization information.
The I and Q signals 18 and 20 are applied to a signal processor 22. The processor calculates either (|2+Q2) or the square root of (|2+Q2). Either resultant signal is a function of the magnitude of the I and Q signals 18 and 20.
The output signal from the processor 22 is applied to an averaging unit 24 which calculates an average of all of the chips occurring during the slots, including the slots in which the synchronization signals of the synchronization symbols occur. A total of 2,560 chips are averaged by the averaging unit 24 when each of the I and Q signals of each synchronization symbol is encoded as 256 chips.
The output of the averaging unit 24 is applied to a control unit 26. The control unit 26 outputs slot timing information which is applied to the synchronization circuits 28 of the demodulator which are well known and accomplish conventional synchronization in response to slot timing information outputted by the control unit.
The prior art demodulator of FIG. 1 has disadvantages. Each of the Golay detectors 12 contains eight delay elements. The sixteen delay elements required to detect the I and Q signals of the synchronization symbol consume power proportional to the number of delay elements. Furthermore, the averaging unit is subject to producing spurious pulses which do not represent synchronization information which can increase the processing load of the control unit 26.